Power-Time Efficient Algorithm for Computing Reconfigurable FFT in Wireless Sensor Network

Wireless sensor network have several constraints, such as a short transmission range, poor processing capabilities, limited available power and slow execution time. The design of algorithms for fast processing of information in sensor network is an emerging research area nowadays. However, due to unique characteristics of the sensor network computing paradigm, the objective is to design algorithms that meet two contradicting goal of low power and fast execution time. In this work, a power-time efficient algorithm is proposed which is implemented with the help of Vedic mathematics for computing FFT (Fast Fourier Transform) over data distributed across smart sensors. The word “Vedic” is derived from the word “veda” which means the store-house of all knowledge. Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing with various branches of mathematics like arithmetic, algebra, geometry etc. Significant reduction in power requirement and delay has been achieved based on the proposed approach. KeywordsWireless Sensor Network, FFT, Vedic Mathematics